1. Field
The present invention relates to a source synchronous system and in particular, a memory controller that controls a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) that is a dynamic random access memory (DRAM) with a high bandwidth (“double data rate”) interface.
2. Background of the Related Art
When the read-write operation in the DDR SDRAM that transmits data in the source synchronous system occurs, a Data Signal (DQ) and Data Strobe Signal (DQS) are transmitted and received between a memory and a memory controller. In such a case, some memory controllers are known to control the delay of the data signal (DQ) and the data strobe signal (DQS).
In computing, Double Data Rate type “three” Synchronous Dynamic Random Access Memory (DDR3 SDRAM) is a modern type of dynamic random access memory (DRAM) that is the higher-speed successor to the DDR and the Double Data Rate type “two” Synchronous Dynamic Random Access Memory (DDR2).
The DDR3 SDRAM adopts “Fly-by Topology” routing the signals in a daisy-chained fashion to improve signal integrity. However, the fly-by topology causes a skew because fly-by topology introduces differences in the wiring length between the memory controller and the memory.
The DDR3 SDRAM has the ability to assist the delay adjustment for reducing the skew. For example, the delay is adjusted by a Write Leveling (WL) command or a command that has an output function of a fixed data (for example, a “predefined pattern” that is defined in the Mode Register 3 (MR3)). Further, it is necessary to set a different delay value to each terminal of the memory controller.
It is possible that only during the initialization of the system, the memory controller can control the WL command and the command that has the output function of a fixed data in the DDR3 SDRAM, and set the delay value separately for each input/output terminal of the memory controller.
However, in the above conventional technique, the transmission of commands are stopped/delayed during a period of read and/or write to the memory and the performance of the system decreases if the memory controller performs the correction for the delay in the same way as the initialization (for example, the WL command) when environmental changes occur after initialization, for example, due to fluctuations in power supply voltage and temperature fluctuations.